The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly it relates to a semiconductor device including an electrode or an interconnect made from a conducting film formed, with a barrier layer disposed therebetween, on an insulating or conducting film provided on a semiconductor substrate and a method for fabricating the same.
Recently, semiconductor integrated circuits having a multi-layer interconnect structure principally made from copper films have been practically used.
A conventional method for fabricating a semiconductor device having a multi-layer interconnect structure principally made from copper films will be described with reference to FIGS. 9A, 9B, 10A and 10B.
First, as shown in FIG. 9A, an insulating film 11 having an interconnect groove is formed on a semiconductor substrate 10 of silicon, and then, a first tantalum nitride film 12 serving as a barrier layer is deposited on the bottom and the walls of the interconnect groove of the insulating film 11. Next, after forming a first copper seed layer 13 on the first tantalum nitride film 12, the first copper seed layer 13 is grown through electroplating so as to form a first copper plating layer 14. Thus, a lower interconnect composed of the first copper seed layer 13 and the first copper plating layer 14 is formed.
Next, after successively depositing a silicon nitride film 15 serving as an adhesion layer and a first interlayer insulating film 16 on the lower interconnect and the insulating film 11, a via hole 17 is formed in the first interlayer insulating film 16 and the silicon nitride film 15. Then, after forming a second interlayer insulating film 18 and a silicon oxide nitrided film 19 serving as an antireflection film on the first interlayer insulating film 16, the second interlayer insulating film 18 is etched by using the silicon oxide nitrided film 19 as a mask, so as to form an interconnect groove 20.
Then, as shown in FIG. 9B, a second tantalum nitride film 21 serving as a barrier layer is deposited on the bottoms and the walls of the via hole 17 and the interconnect groove 20 by reactive sputtering, and thereafter, a second copper seed layer 22 is formed on the second tantalum nitride film 21 by sputtering.
Subsequently, as shown in FIG. 10A, the second copper seed layer 22 is grown through the electroplating so as to form a second copper plating layer 23. Thereafter, portions of the second tantalum nitride film 21, the second copper seed layer 22 and the second copper plating layer 23 present on and above the silicon oxide nitrided film 19 are removed by chemical mechanical polishing (CMP), thereby forming a plug 24 and an upper interconnect 25 composed of the second copper seed layer 22 and the second copper plating layer 23.
However, since the adhesion between the second tantalum nitride film 21 serving as the barrier layer and the upper interconnect composed of the first copper seed layer 22 and the second copper plating layer 23 is not good, peeling is caused between the second tantalum nitride film 21 and the upper interconnect through subsequently conducted annealing, such as annealing for growing a crystal grain of copper. As a result, a void 26 is disadvantageously formed between the plug 24 and the lower interconnect as shown in FIG. 10B.
When the void 26 is formed between the plug 24 and the lower interconnect, the contact resistance between the plug 24 and the lower interconnect is largely increased.